58 replies to this topic

[alacran]

My CPU is i 3225 (third generation) and the microcode for it was updated before spectre and meltdown were discovered, so it do not have any patch for them yet.  Hope Intel publish new updates for microcodes soon, and then I'll check again but it is very possible you are right in this:

 

Nothing unusual, the NT Kernel is loaded before your device driver, and decides what you have, with your result "disabled due to lack of microcode" in time to do anything..

 

If that is the case I found a page with tools to add/delete microcodes to Bios, I do not have the link with me at the moment but it is only for AMI Bios (as mine).

 

alacran

[Mikorist]

Excellent posting by David Woodhouse (He is a Kernel Engineer at Intel.)

 

 

 

I think we've covered the technical part of this now, not that you like
it — not that any of us *like* it. But since the peanut gallery is
paying lots of attention it's probably worth explaining it a little
more for their benefit.

This is all about Spectre variant 2, where the CPU can be tricked into
mispredicting the target of an indirect branch. And I'm specifically
looking at what we can do on *current* hardware, where we're limited to
the hacks they can manage to add in the microcode.

The new microcode from Intel and AMD adds three new features.

One new feature (IBPB) is a complete barrier for branch prediction.
After frobbing this, no branch targets learned earlier are going to be
used. It's kind of expensive (order of magnitude ~4000 cycles).

The second (STIBP) protects a hyperthread sibling from following branch
predictions which were learned on another sibling. You *might* want
this when running unrelated processes in userspace, for example. Or
different VM guests running on HT siblings.

The third feature (IBRS) is more complicated. It's designed to be
set when you enter a more privileged execution mode (i.e. the kernel).
It prevents branch targets learned in a less-privileged execution mode,
BEFORE IT WAS MOST RECENTLY SET, from taking effect. But it's not just
a 'set-and-forget' feature, it also has barrier-like semantics and
needs to be set on *each* entry into the kernel (from userspace or a VM
guest). It's *also* expensive. And a vile hack, but for a while it was
the only option we had.

Even with IBRS, the CPU cannot tell the difference between different
userspace processes, and between different VM guests. So in addition to
IBRS to protect the kernel, we need the full IBPB barrier on context
switch and vmexit. And maybe STIBP while they're running.

Then along came Paul with the cunning plan of "oh, indirect branches
can be exploited? Screw it, let's not have any of *those* then", which
is retpoline. And it's a *lot* faster than frobbing IBRS on every entry
into the kernel. It's a massive performance win.

So now we *mostly* don't need IBRS. We build with retpoline, use IBPB
on context switches/vmexit (which is in the first part of this patch
series before IBRS is added), and we're safe. We even refactored the
patch series to put retpoline first.

But wait, why did I say "mostly"? Well, not everyone has a retpoline
compiler yet... but OK, screw them; they need to update.

Then there's Skylake, and that generation of CPU cores. For complicated
reasons they actually end up being vulnerable not just on indirect
branches, but also on a 'ret' in some circumstances (such as 16+ CALLs
in a deep chain).

The IBRS solution, ugly though it is, did address that. Retpoline
doesn't. There are patches being floated to detect and prevent deep
stacks, and deal with some of the other special cases that bite on SKL,
but those are icky too. And in fact IBRS performance isn't anywhere
near as bad on this generation of CPUs as it is on earlier CPUs
*anyway*, which makes it not quite so insane to *contemplate* using it
as Intel proposed.

That's why my initial idea, as implemented in this RFC patchset, was to
stick with IBRS on Skylake, and use retpoline everywhere else. I'll
give you "garbage patches", but they weren't being "just mindlessly
sent around". If we're going to drop IBRS support and accept the
caveats, then let's do it as a conscious decision having seen what it
would look like, not just drop it quietly because poor Davey is too
scared that Linus might shout at him again.

I have seen *hand-wavy* analyses of the Skylake thing that mean I'm not
actually lying awake at night fretting about it, but nothing concrete
that really says it's OK.

If you view retpoline as a performance optimisation, which is how it
first arrived, then it's rather unconventional to say "well, it only
opens a *little* bit of a security hole but it does go nice and fast so
let's do it".

But fine, I'm content with ditching the use of IBRS to protect the
kernel, and I'm not even surprised. There's a *reason* we put it last
in the series, as both the most contentious and most dispensable part.
I'd be *happier* with a coherent analysis showing Skylake is still OK,
but hey-ho, screw Skylake.

The early part of the series adds the new feature bits and detects when
it can turn KPTI off on non-Meltdown-vulnerable Intel CPUs, and also
supports the IBPB barrier that we need to make retpoline complete. That
much I think we definitely *do* want. There have been a bunch of us
working on this behind the scenes; one of us will probably post that
bit in the next day or so.

I think we also want to expose IBRS to VM guests, even if we don't use
it ourselves. Because Windows guests (and RHEL guests; yay!) do use it.

If we can be done with the shouty part, I'd actually quite like to have
a sensible discussion about when, if ever, we do IBPB on context switch
(ptraceability and dumpable have both been suggested) and when, if
ever, we set STIPB in userspace.

 

https://lkml.org/lkml/2018/1/22/598

[omniplex]

JFTR, Intel found issues in their microcode updates (January 22).

[Mikorist]

 
http://lkml.iu.edu/h...01.2/04628.html

Linus Torvalds 

[Mikorist]

Here is FIX. Will work 200%. But it is "in-silicon" . 

http://www.tomshardw...ctre,36405.html

[Mikorist]

The researchers behind the Spectre  outlined the new Bitcoin protocol in a paper published this week

 

https://eprint.iacr.org/2018/104.pdf

 

New blockchain scalability protocol is builded on SPECTRE (has same name as bug) . Spectre protocol called PHANTOM.

Funny and sad in same time

[alacran]

What is frustrating is: Intel is updating microcode but passing the responsavility to the OEM's to make a new Bios in order to update your processor microcode, and almost all OEM builders of MB's do not plan to update Bioses for MB's older than 3 or maybe 4 years.

But if we remember not so long ago MS made updates for Intel CPUs microcode as you can see:

For XP and Vista: https://support.micr...es-the-reliabil

For 7 and 8: https://support.micr...ate-for-windows

 

As this prove without doubt, it can be done this way, this starts seeming to me more as a way to improve sales of new OS, PC, MB and CPU wich will get the Bios update. (and do no forget new RAM).

 

Finally the damned marketing is the game always.

[Mr B]

As this prove without doubt, it can be done this way, this starts seeming to me more as a way to improve sales of new OS, PC, MB and CPU wich will get the Bios update. (and do no forget new RAM).
 
Finally the damned marketing is the game always.

Not entirely sure about what you are trying to say.
Can Microsoft have the OS load the microcode? Of course. Will they? possibly. They probably already do, unless they found a different way to get the same / better result.

But the problem is... What do you do with what ever loads before the OS? Unless the microcode in in the UEFI, (BIOS) you do not have any boot time protection.
As i've said before. It's quite unlikely that anyone actually will target home users with any of this in a effective way, but a patch should definitely be provided by the motherboard providers. The argument is made that it would cost to much, but in reality... Nope. Just updating the microcode isn't a complicated process, and putting it in the download section with the drivers for your hardware, with a "BETA" disclaimer, would be sufficient.
Hell. People update the microcode in BIOS.rom's just so they can run unsupported Xeon's in consumer boards. It's not that hard. But on a user level we generally have to remove something else to add the new code, with the proper library's that the manufacturer has, this could be omitted.

[Mikorist]

MS made updates for Intel CPUs microcode

 

And right now MS offering a new option. Update to disable mitigation against Spectre:

 

https://support.micr...ectre-variant-2

 

To prevent unpredictable system behaviors. 

 

Crazy completely.